Memory modules, or “multichip modules” have become a popular method for packaging memory in computer systems, since the module can provide significantly higher memory density than is currently available from a single memory device. The multichip module generally consists of a plurality of individual memory devices of a uniform design that are supported on an interconnecting substrate such as a printed wire board (PWB). Although the multichip module may have all of the memory devices positioned on a single side of the PWB, “mirrored board” multichip modules that have memory devices positioned on both sides of a PWB are preferred, since the mirrored board module advantageously permits the available surface area of the PWB to be more fully utilized.
FIG. 1 is a block diagram of a computer system 10 according to the prior art, which includes one or more multichip memory modules, as previously described. Briefly, and in general terms, the system 10 includes a processing unit 12 capable of performing general-purpose arithmetic, logic and control functions. The processing unit 12 is coupled to a memory controller 16 that receives memory requests from the processor 12, which may include a memory command, such as a read command, as well as an address that designates the location from which data and/or instructions are to be read. The memory controller 16 uses the command and address to generate appropriate command signals as well as row and column signals. The memory controller 16 is coupled to one or more multichip modules 14 through an interconnecting bus 18, which generally includes one or more control lines 11 that permit the exchange of control signals between the memory controller 16 and the modules 14. The bus 18 also generally includes one or more data lines 13 to provide a data path between the memory controller 16 and the modules 14. One or more address lines 15 are similarly present in the bus 18 that permit the source, or destination of data transmitted on the bus 18 to be designated.
Turning now to FIG. 2, a block diagram of a memory device 22 according to the prior art is shown, that comprises a portion of the memory capacity in the one or more multichip modules 14, as shown in FIG. 1. The device 22 is generally configured to store information in an array format. Accordingly, the device 22 is adapted to accept row and column address signals A0–A11 at address terminals 23 to permit the identification of an individual storage location within the device 22. The device 22 is further configured to exchange data signals DQ0–DQ 16 with the system 10 (as shown in FIG. 1) at data terminals 25 subsequent to the identification of the storage location. A plurality of control signals may also be transferred to the device 22 from the system 10 (as shown in FIG. 1) at control signal terminals 26 to control the operation of the device 22. For example, a clock signal (CLK), a row address strobe signal (RAS), a column address strobe signal (CAS), a write-enable signal (WE), a chip select signal (CS), and a chip enable signal (CE) are examples of control signals that are commonly transferred to the device 22 to properly order the operation of the device 22. In addition, various power inputs, which generally include a voltage input and a ground connection, may be coupled to the device 22 at power input terminals 27.
Still referring to FIG. 2, a portion of the signals coupled to the device 22 are generally functionally interchangeable, because the signals provide compatible information and/or data to the device 22. For example, row address signals may be strobed into the device 22 responsive to the RAS signal, and column address signals may similarly be strobed into the device 22 responsive to the CAS signal, to specify a particular memory location within the device. If the row address signals or the column address signals are interchanged, so that the row address signals are latched by the CAS signal and the column address signals are latched by the RAS signals, the device remains functional (although a different memory location is specified) because the row and column address signals are functionally compatible. The data input/output signals 25 are similarly functionally compatible, and may be interchanged in an analogous manner. In contrast, other signals coupled to the device 22 do not exhibit the foregoing functional compatibility. The control signals 26 may not, in general, be interchanged. For example, if the RAS signal is interchanged with the CAS signal, the device 22 would be rendered inoperative, since the RAS and the CAS signals are not functionally compatible. Moreover, if either the RAS or the CAS signals is interchanged with the CL signal, for example, the device 22 would similarly be rendered inoperative.
FIG. 3 is a partial plan view of a mirrored board multichip module 14 for the system 10 according to the prior art. The module 14 generally includes a plurality of memory devices 22 positioned on opposing sides of a PWB 30 that are interconnected by a plurality of traces 32 formed on the opposing surfaces of the PWB 30. for clarity of illustration, only a portion of the plurality of traces 32 are shown in FIG. 3. The traces 32 may be also be formed in an interior portion of the PWB 30. The PWB 30 further includes a edge connector 34 that extends along a portion of an edge of the PWB 30 that allows at least a portion of the traces 32 to be coupled to the bus 18, as shown in FIG. 1.
FIG. 4 is a partial cross sectional view of the mirrored board multichip module 14 according to the prior art viewed at a location indicated by section 4—4 of FIG. 3. As previously described, the module 14 includes a plurality of memory devices 22 positioned on opposing sides of the PWB 30 that may be interconnected to cooperatively form the module 14. Accordingly, the module 14 generally includes a plurality of interconnecting portions 36 that permit connection terminals 35 that carry compatible signals to be electrically interconnected. Since the devices 22 are generally substantially identical, the interconnecting portion 36 generally includes an extension length 38 that extends along a portion of the PWB 30 in order to electrically interconnect the connection terminals 35.
One disadvantage present in the prior art mirrored board multichip module 14 is that the extension length 38 as shown in FIG. 4 increases the overall length of the signal path. Thus, when the system 10 (as shown in FIG. 1) operates at elevated frequencies, the additional signal path length presented by the extension length 38 may adversely affect the overall performance of the module 14. For example, signal delays introduced by the additional extension length 38 may degrade the performance of the module 14, and thereby affect the performance of the entire system 10. Still further, the extension length 38 may introduce parasitic inductances and/or capacitances that may cause an impedance mismatch to occur between the device 22 and other portions of the system 10, that may cause a signal transmitted along a signal path containing the extension length 38 to be partially reflected. In particular, the short rise times associated with digital signals may further exacerbate this problem.
One prior art approach is to package the memory devices in reversed image pairs, so that the connection members of the respective memory devices are mirror images. Consequently, when the memory devices are positioned on opposing surfaces of the PWB, the connection members of the respective memory devices memory are substantially opposed, so that the extension 38 of the interconnecting portion 36 may be eliminated, thus allowing signal-compatible terminals of the device to connect by vias that extend through the PWB. An example of a memory device having the foregoing reversed image characteristics are the M5M410092BFP and M5M410092BRF memory devices, manufactured by the Mitsubishi Electric and Electronics, Inc. of Sunnyvale, Calif.
Although the foregoing reversed image memory devices permit the devices to be interconnected when positioned on opposing surfaces of a PWB, a disadvantage of this approach is that virtually identical memory devices must be packaged in different packages, which generally increases inventory requirements and production costs, so that the overall cost associated with the fabrication of the memory module is adversely affected.
Accordingly, there is a need in the art for a memory device that may be positioned on either surface of a mirrored board memory module without substantially increasing the length of the interconnecting portions that couple signal-compatible terminals of the devices. Further, there is a need in the art for a device that may be readily configured so that the memory device may be positioned on either surface of a mirrored board memory module without incurring additional signal path lengths to the module that may degrade the performance on the opposing surfaces of the PWB.